Silicon dioxide (SiO2) forms the basis of the planar technology. In industrial practice the dielectric coatings for electronic and photonic devices are most frequently formed by thermal oxidation of silicon (Si) in dry or wet oxygen ambient at temperatures ranging from 900° C. to 1200° C. SiO2 is also deposited by chemical vapor deposition (CVD) techniques at lower temperatures (200-900° C.) on various substrates.
Thermal and CVD-grown SiO2 based layers are used as diffusion masks, to passivate device junctions, as electric insulation, as dielectric material in Si technology, and as capping layers for implantation-activation annealing in III-V compound semiconductor technology. For high efficiency crystalline silicon solar cell applications, thin film SiO2 layers are used for front and back surface passivation and as the first layer antireflection coating (ARC) in a multi layer ARC structure.
The growth of dielectric films at low temperatures is very attractive for most device applications due to reduced capital cost, high output, as well as the technological constraints associated with the growth of dielectric thin films using conventional high-temperature growth/deposition techniques. Thin dielectric film near room-temperature growth/deposition techniques are known in the art and are chiefly used for microelectronic/photonic (optoelectronic) device applications. An example of these low temperature methods are the physical vapor deposition processes which include: nonreactive (conventional) or reactive resistive, induction or electron beam evaporation, reactive or nonreactive dc or RF magnetron and ion-beam sputtering processes.
The room temperature growth of dielectric layers on semiconductor surfaces using anodic oxidation is well known. It can grow SiO2 layers on Si substrates that are up to 200 nm thick, consuming a portion of the underlying silicon layer in the process. Unfortunately, anodic oxidation is not compatible with metallization schemes, limiting its application as a replacement of thermal grown or CVD deposited SiO2.
The use of organo-metallic solutions to deposit SiO2 dielectric layers is known in the art. The dielectric layer is applied either by dipping the substrate into the organo-metallic solution, by spraying the organo-metallic solution on the substrate, or by spinning the substrate after a small amount of the organo-metallic solution is applied to it. After the organo-metallic solution is applied, it is necessary to drive off the solvent part of the solution by heating the substrate to ˜400° C.
A large number of patents, patent applications, and published papers describe near room temperature related processes for the deposition of SiO2 and SiO2-XFX layers on various substrates, including silicon surfaces. The so called liquid-phase deposited (LPD) SiO2 technique was initially developed in 1950 for depositing SiO2 on the surface of soda lime silicate glass. LPD is based on the chemical reaction of H2SiF6 with water to form hydrofluoric acid and solid SiO2. The H2SiF6 solution is initially saturated with SiO2 powder (usually in a sol-gel from). Before immersing the glass into the solution a reagent that reacts with the hydrofluorosilicilic acid, such as boric acid, may be added to the solution to supersaturate with silica. The LPD process is a competition between the deposition and etching of SiO2. Regardless of the small variations in formulations, the overall reversible chemical reaction is:H2SiF6+2H2O 6HF+SiO2 
One of the major disadvantages of the SiO2 LPD method described above is a very low deposition rate. Using hydrofluorosilicilic acid, SiO2-XFX (x is ˜2%), deposition rates of 110 nm/hr have been reported. These deposition rates are far too low for practical ARC applications; it would require more than one hour to deposit a nearly optimal ARC thickness of 130 nm for solar cell applications.
High Growth Rate RTWCG SiOX Thin Film Dielectrics
U.S. Pat. No. 6,080,683, entitled “Room Temperature Wet Chemical Growth Process of SiO Based Oxides on Silicon” and U.S. Pat. No. 6,593,077 entitled “Method of Making Thin Films Dielectrics Using a Process for Room Temperature Wet Chemical Growth of SiO Based Oxides on a Substrate”, describe a RTWCG SiOx method and process on a semiconductor substrate comprising:                i. providing a reaction mixture comprising of a silicon source, a pyridine compound, and an aqueous reduction oxidation solution;        ii. a catalyst to enhance the reaction;        iii. reacting the mixture with the substrate to form said silicon oxide layer.        
High growth rate RTWCG SiOX thin films, as revealed in U.S. Pat. No. 6,080,683 and U.S. Pat. No. 6,593,077 were grown using the RTWCG process on silicon and other semiconductor substrates using commercial-grade 34% H2SiF6. High growth-rate growth of SiOX oxide on silicon substrates was achieved by using commercial grade organic and inorganic silicon sources, a pyridine compound (i.e. N-(n-Butyl)pyridinium chloride), redox aqueous solutions based on Fe2+/Fe3, an organic or inorganic homogeneous co-catalyst, and non-invasive additives including NaF, KOH, NH4F, and HF(aq). In U.S. Pat. No. 6,613,697, the organic components of the growth solution were substituted with inorganic components. The RTWCG SiOX thin film layers grew on various semiconductor substrates at a higher growth rate and with lower metallic and non-metallic impurity concentration. Also, there was an improvement in the dielectric properties of the resulting thin films when compared to the RTWCG SiOX thin films grown in solutions with organic components.
By using the above growth solution formulations, the RTWCG SiOX growth rate on Si surfaces ranges from 1 nm/min to over 100 nm/min, depending on the composition of the growth solution.
Antireflection Coatings Prior Art
Antireflection coatings (ARC) are included in a solar cell design to substantially reduce the amount of reflected light. Bare Si loses 42% of light with long wavelengths of 1.1 μm, 37% of light with wavelengths of 1 μm, and about 54% of light with short wavelengths of 0.4 μm. A textured front surface, such as regularly spaced pyramids or porous silicon (PS), can lower the AM 1.5 average weighted reflection to 12-18% over the 0.4 μm-1.2 μm wavelength range.
The optimal thickness of an antireflection coating is calculated by the following formula:
      d    1    =            λ      0              4      ⁢                          ⁢              n        1            For a quarter wavelength ARC made of a transparent material having a refractive index n1, and a light incident on the coating with a free-space wavelength λ0, the thickness which causes minimum reflection is d1. Because the index of refraction is wavelength-dependent, near zero reflection can only occur for a single wavelength. The refractive index and thickness of an ARC must minimize the reflection of light with wavelengths of 0.6 μm since this wavelength is close to the peak power of the solar spectrum. While the equations for multiple antireflection coatings are more complicated than that for a single layer, by properly adjusting the refractive index and thickness of two layers it is theoretically possible to produce two minima and an overall reflectance as low as 3%.
A proper SLAR on smooth surfaces (e.g. MgF2, SiO2, SiO, SiNx, TiO2 and Ta2O5) can reduce the AM1.5 average weighted reflection (AWR) to 12-16% over the 0.4-1.1 μm wavelength range. For an optimized CVD-deposited SiNx ARC, which is becoming the norm for silicon solar cell ARC applications, the AM1.5 AWR is ˜12% with a simulated minimum AWR of 10.4% as calculated by Wright et al on flat c-Si having an assumed film index of refraction, n, of 1.95, and thickness, d, of 81 nm.
Whether or not the simulated minimum SiNx SLAR AWR is achievable in a production environment remains to be seen. But even if the simulated reflectance is achieved, the reflective losses are still too high at 10.4% reflectivity. The industry still needs a practical low-cost way of further lowering the reflectance through a double layer ARC, a textured silicon solar cell surface, or both. However, this approach becomes cost prohibitive for most commercial solar cell applications.
For textured surfaces with well designed single or double layer ARCs such as ITO/SiO2, ZnS/MgF2, TiO2/MgF2, and TiO2/Al2O3, the AM1.5 AWR has been brought down to between 3% and 8%. A large number of studies on double layer ARCs have been reported. The most stable configuration with respect to variations in film thicknesses have been found to be designs with a high refractive index (n) on the substrate and a low refractive index towards the ambient.
Depositing uniform ARCs on textured surfaces is problematic. The nanometer-sized features of a polysilicon structure make it difficult to deposit or grow uniform ARC through conventional techniques. Certain cell manufacturers do not use an ARC due to this issue; the penalty they pay is up to a 10% relative loss in efficiency along with surface stability problems.
Selective Emitter Prior Art
Currently, screen-printed silicon solar cells utilize n+/p emitters that are diffused to have sheet resistances in the 40-60 Ω/sq range, and surface doping concentrations that are greater than 2×1020 cm−3. A high surface doping and low sheet resistance is necessary to achieve an acceptable contact resistance of around 1 μΩ-cm2 as well as low junction shunting and recombination in the space charge region. However, emitters of this type have low open-circuit voltages (high surface recombination for emitters with high surface doping and Auger recombination) as well as poor short-circuit currents due to a poor blue response (high-emitter recombination and free-carrier absorption). Good screen-printed contacts with a contact resistance of ˜1.0×10−4 Ω-cm2, emitters with a sheet resistance greater than 100 Ω/sq, and surface doping at around 1019 cm−3 are the main tasks in developing high efficiency industrial solar cells.
To reduce manufacturing costs, industrial techniques used for front-contact fabrication require a deep and highly doped junction for acceptably low contact resistance and to avoid metallic impurity penetration toward the junction, space charge, and bulk emitter regions. The typical emitter sheet resistance used in a conventional screen printing metallization process is 50-80 Ω/sq. Small-scale manufacturing employs POCl3 or solid P2O5 dopant sources and open tube furnaces to carry out the diffusions. Large scale manufacturing employs screen printing, spray-on, or spin-on of various phosphorus-containing paste and liquid-dopant sources followed by conveyor belt furnace diffusion.
The emitter sheet resistance of cells that do not possess a good quality selective emitter is between 50-80 Ω/sq and their fill factor (FF) is usually less than 76%. The lower FF of cells with higher emitter sheet resistance is due to a high contact resistance, a high lateral emitter resistance, and the associated low metal conductivity of screen-printed contacts. In order to gain the full performance benefit from improved emitter surface passivation, it is necessary to design the emitter doping profile so that it is lightly doped between gridlines, yet heavily doped underneath them. This is especially true for conventional industrial solar cells with screen-printed gridlines which require a heavily doped substrate beneath them for acceptably low contact resistance.
Cells with a selective emitter have a larger short circuit current (Isc) since the dead layer is removed from the active emitter surfaces. Also beneficial is the passivation of the emitter's surface, so that the bulk dark current (Job) is the controlling limiting factor of the open circuit voltage (Voc). Improved conductivity under the grid lines lowers the series resistance while the shunt resistance increases due to the extra margin of protection that the deeper junction in the grid area offers against the partial “punch-thru” of the grid metal. Since the silicon underneath the grid lines is more highly conductive, narrower lines can be utilized which can be spread further apart, resulting in a smaller grid shadow area.
In the case of screen-printing, a selective emitter is difficult to achieve especially through a one-step process. There has been a delay-in-implementation of the very important SE efficiency enhancement feature because this selectively-patterned emitter doping profile has historically been obtained using expensive photolithographic or advanced screen-printed alignment techniques along with multiple high-temperature diffusion steps
Conventional SE techniques can be divided into three main categories:                a. selective emitter cells fabricated via masking and etching with no alignment;        b. selective emitter cells fabricated by self-alignment without the need for masking or etching;        c. selective emitter cells fabricated by self-aligned self-doping Ag pastes.Techniques (a) and (b) are generally time consuming and somewhat expensive. Technique (c) is not trivial because the diffusivity of Ag in Si is higher than that of P, which can lead to a high junction leakage current and high junction ideality factor.High Efficiency Crystalline Silicon Solar Cells        
A low-cost and highly-efficient solar cell is the key to large-scale acceptability of photovoltaic (PV) systems. Redesigned small area solar cells with new materials and process step technologies, have produced many laboratory cell schemes resulting in cell efficiencies of over 20%. Two small area laboratory scale approaches, initially used by niche markets such as solar cars, are the passivated emitter with rear locally diffused (PERL) cell, and the interdigitated back contact (IBC) cell. Although these and other laboratory cell designs have been pushing up the efficiency of c-Si solar cells, to date, none of these cell designs use, low-cost, solar-grade silicon substrates, and only few of them use low-cost fabrication technology process steps such as screen printing metallization.
The development of high efficiency silicon solar cells not only targets efficiency increases but also cost savings. Of importance to cost savings is the number and complexity of process steps, material consumption, and energy consumption needed to produce a unit of installed peak power. Other important considerations in choosing the winning technologies include environment aspects as well as standards and manufacturing engineering such as process automation and control.